U.S. Pat. No. 4,099,196 shows an electrically alterable PROM which incorporates a floating polysilicon gate and a programming gate in the metal-oxide-semiconductor (MOS) environment. The floating gate is either positively (lack of electrons) charged or negatively charged to provide threshold voltages of approximately -10 V and 10 V, respectively, for the MOS device.
Similarly, U.S. Pat. No. 4,164,751 shows an MOS memory cell device wherein an oxide capacitance and a depletion capacitance are obtained, in the instance of the former, by the interaction of an electrode with the surface of a substrate and, in the instance of the latter due to the interaction of double ion implantations within the substrate.
U.S. Pat. No. 4,163,243 shows a one device memory cell arrangement wherein the depletion layer capacitance is increased by locally enhancing the substrate dopant concentration.
U.S. Pat. No. 4,217,601 shows a field effect transistor memory cell which incorporates a trapping layer into which electrons are injected to control current flow between the source and drain of the associated field effect transistor.
None of the above described devices uses a floating electrode to vary the effective capacitance of a structure from one effective capacitance when no electrons are present on it to a different effective capacitance when electrons are present on the floating electrode. Some prior art structures use capacitors of a fixed character to store charge and to move about by means of an associated FET. Other prior structures store injected charge at interfaces to influence the conduction or nonconduction of an associated transistor. Indeed, none of the prior art patents teach or suggest that the rather complex memory cells of the prior art which include field effect transistors and the like can be considerably simplified by invoking the varying capacitance effect provided by the structures of the present invention.
It is, therefore, an object of the present invention to provide a simplified memory cell or storage device which requires no transistors within the memory cell itself.
It is another object of the present invention to provide a memory cell in which the injection of electrons onto a single crystal floating electrode changes the capacitance of the structure from the capacitance it had when no electrons are present.
A further object of the present invention is to provide a memory cell wherein the state of the memory cell is sensed capacitively.